Design of digital blocks with minimum energy consumption

In this article describes the problem of energy units with digital technology CMOS (complementary metal-oxide-semiconductor. A distinctive feature of these schemes compared to bipolar technologies (TTL, ECL, etc.) is a very low power consumption in static mode. Another feature of CMOS structure compared to other it`s availability n-, and p-channel field-effect transistors; as a result CMOS circuits with higher performance and lower power consumption, but this value can further reduce the expense of true design.