Designing of Multi Clock FIFO Buffer for Netwwork On Chip

FIFO is implies first in first out using queue methodology for memories read and write of any information and data using some control logic. The whole work of FIFO is fully dependent on the control circuitry and clock domain. It is often used to control the flow of data from source to destination by the transition of every clock. Basically FIFO differentiate by clock domain either Synchronous or Asynchronous. There are various methods to design and synthesized FIFO but here full focus is on the memory which is used to store the data in domain of clock either sync. and async. or single and multiple clock cycles.This paper will differentiate the design, synthesize and analyze an Asynchronous FIFO using Register file memory by older version of Synchronous FIFO. This paper concludes the effect of using register file instead of random access memory for storage of data in FIFO memory. Various parameters are considered in this paper like on-chip components (clock, signal, input and outputs etc), clock domain, type of resources, minimization? and optimization of? hierarchy of the device.The RTL description for the FIFO is written using Verilog HDL (hardware description language) . Design is simulated and synthesized using ISim Simulator and Xilinx ISE Design suite 12.4.