AREA OPTIMIZATION OF SPI MODULE USING VERILOG HDL

The Objective of this Paper is to optimize the area of (Serial peripheral interface) SPI module. SPI is a inter and intra communication protocol used for communication and testing’s like BST. Its occupies space in Embedded industry for communication of devices like Microcontrollers, peripheral’s for example ADC’s, DAC’s, Memories etc. ll these devices have a SPI module on it which acts as a master or Slave. This module is consuming more Area, here we made a approach in order to reduce Area, which reduces Cost as well. Protocol is implemented in Structural Code Verilog, Simulated and Synthesized Using Xilinx9.1 on various families of FPGA. Finally whole design is mapped onto Vertex 5 FPGA.