DESIGN AND IMPLEMENTATION OF HIGH SPEED AES ALGORITHM FOR DATA SECURITY

In the current cyber era, 44% of the Indians use internet today and the numbers are increasing exponentially in recent years. It is accepted truth that in the coming year’s security architecture in cyberspace decides growth of nation. In this paper, we present a VLSI based AES (Advanced Encryption Standard) encryption that effectively addresses espionage and fraudulent cybercrime based cyber attacks. It is most commonly used symmetric block cipher algorithm that transform information into obscure data based on key-defined transformation set. In addition, it is lossless operation with size of input and output being the same and could be extended to a wide range of applications. We limit our focus to128-bit AES encoding and decoding operations over VHDL coded transformation that requires key for successful completion of the operation With rise in several methods proposed for implementation of data security it has become more vital for a feasibility study of any hardware design is essential i.e. to test encryption and decryption process of the proposed 128-bit AES algorithm. In the simulations results, we analyze the each of the transformation that is incorporated for coding on FPGA using Xilinx ISE tool.