DESIGN OF LOW-POWER FULL ADDER IN 0.18 ?m CMOS TECHNOLOGY

With the increase in device integration level and the growth in complexity of Integrated circuits, small delay and low power dissipation become important parameters as these increases performance and portability. Battery storage is limited, to extend battery life; low power operation is the primary requirement in integrated circuits. Furthermore, high speed and multiple parallel applications need high computing power, placing greater demands on energy storage elements within the system. Large power dissipation in high performance digital systems requires large size heat sinks. These off chip component makes chip bulky and require large space. Secondly, extra heat in integrated circuit degrades the system performance. The full adder (FA) is a very important and basic building block in Arithmetic and Logic unit (ALU) of digital processor. The most widely accepted metrics to measure the quality of a digital circuit or to compare various circuit styles is power delay product. Further, Portability imposes a strict limitation on power dissipation while needs more computational speeds. The reduced power consumption and the improved speed require optimizations at all levels of the design procedure. CMOS technology has low power dissipation. Many researchers have developed various logic styles to implement Full Adder such as conventional static CMOS, dynamic CMOS, transmission gates, NORA[38] which has various advantages and limitation. Conventional Static CMOS has been used in much processor design. Static Pass Transistor circuit can also be used for Low Power applications. Dynamic circuit is also useful in Low Power high speed systems with careful clocking. Reversible logic is also noticeable recently for reducing the power dissipation. Quantum arithmetic component design requires reversible logic circuits. Reversible logic circuits has several applications such as in low power digital design, nanotechnology , DNA and quantum computing. In the proposed work, the limitation associated with the above mentioned design style are studied and the transistor count reduction is done to reduce the power dissipation. The newly proposed structures will be simulated using SYMICA simulator software and 0.18 ?m CMOS technology is selected for simulation. The proposed design will definitely reduce the power dissipation at-least 20%.