AN EMBEDDED ARCHITECTURE FOR FEATURE DETECTION USING MODIFIED SIFT ALGORITHM

In video analytic and computer vision systems, image feature detection and matching is the fundamental task in object recognition, image indexing, visual localization etc. These processes establishes the correspondence between two images taken at different time. To most of the embedded systems, the challenge is its large complexity in computation. Real-time performance is a critical demand to most of these applications, which require the detection and matching of the visual features in real time. The thesis work proposes a new FPGA-based embedded architecture for image feature detection. In this the Scale Invariant Feature Transform (SIFT) feature detector is used to reduce the utilization of FPGA resources. The correspondence point pairs obtained can be either used in an embedded application or accessed via Ethernet for remotely computer vision applications. Here a modified Gaussian filter is used for keypoint detection, in which the adder-multiplier sections are fused by using a modified Booth recoder design. This design will increase the performance of the whole system with considerable reduction in delay, power consumption and hardware complexities. The detected feature keypoints from the image can be described using feature descriptor module. The binary stream of bits are obtained from the description section and finally a feature matching process is done to identify whether the two images taken at two different time were matched or not. The software used for the work is Xilinx ISE Design Suite with Verilog coding.