DESIGN AND IMPLEMENTATION OF EMBEDDED HARDWARE ACCELERATOR FOR DIAGNOSING HDL-CODE IN ASSERTION-BASED VERIFICATION ENVIRONMENT

The use of assertions for monitoring the designer's intention in hardware description language (HDL) model is gaining popularity as it helps the designer to observe internal errors at the output ports of the device under verification. During verification assertions are synthesised and the generated data are represented in a tabular forms. The amount of data generated can be enormous depending on the size of the code and the number of modules that constitute the code. Furthermore, to manually inspect these data and diagnose the module with functional violation is a time consuming process which negatively affects the overall product development time. To locate the module with functional violation within acceptable diagnostic time, the data processing and analysis procedure must be accelerated. In this paper a multi-array processor (hardware accelerator) was designed and implemented in Virtex6 field programmable gate array (FPGA) and it can be integrated into verification environment. The design was captured in very high speed integrated circuit HDL (VHDL). The design was synthesised with Xilinx design suite ISE 13.1 and simulated with Xilinx ISIM. The multi-array processor (MAP) executes three logical operations (AND, OR, XOR) and a one's compaction operation on array of data in parallel. An improvement in processing and analysis time was recorded as compared to the manual procedure after the multi-array processor was integrated into the verification environment. It was also found that the multi-array processor which was developed as an Intellectual Property (IP) core can also be used in applications where output responses and golden model that are represented in the form of matrices can be compared for searching, recognition and decision-making.