Implementation of High Speed & Area Efficient Modified Booth Recoder for Efficient Design of the Add-Multiply Operator using VHDL

Many communication applications require multifaceted arithmetic operation are used in many digital signal processing (DSP) relevance. Mainly in the reduction of multiplier power and area consumption it can play an important role in high performance of any digital indication processing system. within this paper, mainly centre of attention on optimizing and increased performance by reduction in power consumption in propose of the fused Add-Multiply (FAM) operator. This implements a new technique by straight recoding of sum two numbers in Modified Booth (MB) form. In this paper implemented a new and efficient structured technique by straight recoding of sum of two numbers by considering existing modified booth (MB) technique. The new technique is implemented by three new dissimilar schemes by integrating them within existing FAM plans. The performance of the proposed three different schemes with the implementation of new model carry select adder (K-adders) gives reduction in conditions of critical delay, hardware complication and power utilization while comparing with the existing AM design.