Area Efficient Architecture for Convolution Using Vedic Mathematics

Convolution is a formal mathematical operation, just as multiplication, addition, and integration. Addition takes two numbers and produces a third number, while convolution takes two signals and produces a third signal. Convolution is used in the mathematics of many fields, such as probability and statistics. In linear systems, convolution is used to describe the relationship between three signals of interest: the input signal, the impulse response, and the output signal. Vedic mathematics is used since it reduces time, increases speeed and is easy to implement. It helps to solve problem 10-15 times faster. It covers explanation of several mathematical terms such as algebra, arithmetic , geometry etcThis paper presents a direct method of reducing convolution processing time using hardware computing and implementations of discrete linear convolution of two finite length sequences (NXN) The purpose of this research is to prove the feasibility of an application specific integrated circuit (ASIC) that performs a convolution on an acquired image in real time. The proposed implementation uses a modified hierarchical design approach, which efficiently and accurately speeds up computation; reduces power, hardware resources, and area significantly. The efficiency of the proposed convolution circuit is tested by embedding it in a top level FPGA .It also provides the necessary modularity, expandability, and regularity to form different convolutions for any number of bits.