Low Power and Area Optimized VHDL Implementation of AES

In this era of information, need for protection of data is more pronounced than ever. Secure communication is necessary to protect sensitive information in military and government institutions as well as private individuals. Current encryption standards are used to encrypt and protect data not only during transmission but storage as well. Data Encryption Standard was introduced in early 1970s as a standard cryptographic algorithm to protect data. However, due to its short 56-bit key length, simple brute force attacks cracked it in less than 10 hrs. Another disadvantage was also the possibility of weak and semi weak keys. In the year 2000, Rijndael Encryption algorithm or AES was chosen by National Institute of Standards and Technology (NIST) to be adopted by the U.S. Government as the new Encryption standard to replace the outdated and easily crackable DES. The major advantage lay in the non-linearity of the key schedule which eliminated the possibility of weak and semi weak keys. This encryption algorithm is virtually crack-proof till date. It is more computationally robust compared with previous algorithms and the security level is higher. However the execution time required is more because of long calculations and several iterations. The goal of this project is to study AES and improve the performance of this algorithm in terms of speed, area and power. In this paper the concept of pipelining for maintaining the speed of encryption is introduced. This design has been implemented in VHDL using Xilinx ISE 14.2i platform.