Low Power and Low Dead Zone Phase Frequency Detector in PLL.Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.3, No. 3)
Publication Date: 2014-03-30
Authors : Jaimini Prajapati; Kiran Patel; Kruti Thakor; Nilesh Patel;
Page : 1154-1158
Keywords : Mentor Graphics; CMOS; DPLL; PFD;
This article presents Low power and Low Dead Zone Phase Frequency Detector for phase locked loop feedback system. It describes a design of a Phase Frequency Detector (PFD) using AND Gate and NOR Gate for 50 MHz and 500MHz frequency and also the comparative analysis of power dissipation and Dead Zone for 50MHz and 500MHz frequency. The Phase Frequency Detector is operated at 1.8V power supply. The proposed architecture of PFD has been implemented using 0.18?m CMOS Technology in ELDO- Mentor Graphics tool.
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Last modified: 2014-05-20 22:18:26