ResearchBib Share Your Research, Maximize Your Social Impacts
Sign for Notice Everyday Sign up >> Login

Implementation of High Performance Comparator in 90nm Technology.

Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.3, No. 3)

Publication Date:

Authors : ; ;

Page : 1378-1381

Keywords : Buffer stage; current sensing comparator; latch comparator.;

Source : Downloadexternal Find it from : Google Scholarexternal


In this paper a CMOS Differential current sensing comparator along with the Buffer stage has been introduced. In this paper comparator is implemented in a standard TSMC 90nm CMOS technology using Mentor Graphics Tool The simulation is carried out in 90nm technology. The supply voltage for this comparator is ± 0.9v. This paper firstly elaborate about basic introduction of Comparator. Next section elaborate Different Current Sensing Comparator and Buffer Stage. Next section elaborate the design of comparator . Last section consist simulation results.

Last modified: 2014-05-26 15:11:45