Optimized Design of Digital Phase Locked Loops for RF Carrier AcquisitionJournal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.3, No. 5)
Publication Date: 2014-05-30
Authors : Abhilasha N.S;
Page : 665-670
Keywords : DPLL; Loop filter; VCO; Mixer; Phase detector; FPGA; Noise.;
This paper presents optimized implementation of Digital Phase Locked Loops (DPLL) for generating RF carrier signal used for phase demodulation. The method used for designing DPLL is based on linear control theory and the receiver is phase locked at higher radio frequency signal which is highly noisy. The building blocks of DPLL such as loop filter are implemented with a new method in digital domain for better noise rejection and accuracy. The paper aims to offer aided acquisition of RF signal with fast frequency and phase locking. The designed DPLL is used for higher frequency range applications of the order of GHz and theoretically expected frequency response graph of the filter is verified practically. HDL programming language is used for coding and simulation.
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Last modified: 2014-06-09 16:43:32