64 Bytes Cell Sized Distributed Packet Buffers for High-Bandwidth Routers?

Performance based routers rely on optimized packet buffers that support multiple queues and provide large capacity and short response time by combining hierarchical buffer architectures of SRAM/DRAM to meet performance based challenges but these architectures suffer from either larger SRAM requirement or higher time-complexity in the memory management. In this paper we propose a scalable and novel 64 bytes distributed packet buffer architecture which resolves the fundamental issues such as how to minimize the overhead of an individual packet buffer and how to design scalable packet buffers that uses independent buffer subsystems for which we first designing an efficient compact buffer that reduces the SRAM size requirement by (n(n-1))/2 and then we introduce a feasible way of coordinating multiple subsystems with a load-balancing algorithm that maximizes the overall system performance which are proved in both theoretically and with practical experimental results that demonstrates our load-balancing algorithm and the distributed packet buffer architecture can be easily scaled to meet the buffering needs of high performance bandwidth links and satisfy the requirements of scaling and support for multiple queues.