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Simulation and Synthesis for TACIT Network Security in Hardware Description Language Environment

Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.3, No. 9)

Publication Date:

Authors : ; ;

Page : 547-555

Keywords : Application Specific Integrated circuits (ASIC); Field Programmable Gate Array (FPGA); Network on chip (NOC); System on chip (SOC); Very High Speed Integrated Circuit hardware Description language (VHDL).;

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In cryptography, it is necessary to encrypt and decrypt the data for code storage and security. Sometimes it is very difficult to secure physically all access networks. The research paper has introduced a new block cipher cryptographic symmetric key algorithm named “TACIT Encryption and Decryption Technique” and its implementation in hardware description language environment. There are already many algorithms supporting to encryption and decryption process over networks, but limited to their block size and key size. In the new TACIT network security algorithm, the key size and text size may be of ‘n’ bits and it provides better results if key size is larger than block size. In the research, it is emphasized to develop chip for network security and it verified by experimentation on Sparten-3 FPGA synthesis. It is possible to enhance network performance and security by exploiting modern features in Field Programmable Gate Arrays (FPGA), which allow the modeling of encryption and decryption algorithm on System-on-Programmable-Chip (SOPC). The work is carried out on modeling and simulation tools, Xilinx ISE 14.2 and Model SimEE 10.1b student’s edition of Mentor Graphics Company.

Last modified: 2014-10-16 22:23:39