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Journal: International Journal of Advanced Research in Engineering and Technology (IJARET) (Vol.12, No. 03)

Publication Date:

Authors : ;

Page : 461-471

Keywords : MD5; Hash function; Throughput; FPGA;

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We defined the hash algorithm as a security object during data transmission. The hash features are 4 more types 1. Message digest (MD5) 2. RIPMED (Race Integrated primitivity of Message Digest) 3. SHA (Secured Hash Function) 4. WHIRLPOOL. From this group of hashes, Message Digest 5 is mostly using in embedded security systems. To obtain high frequency and throughput in regions of Area, frequency and throughput by using unfolding transformation technique factor of 2. To get better outcomes to overcome the dis-advantages of existing method, the proposed design is reduced the data fetching stages from 32 to 16 stages. However, the overall process is speedy than the existing algorithm. And this work will explore the possibilities of increasing the speed of bruteforce attack on FPGA implementation of MD5 algorithm. The proposed design/method in FPGA to parallelize the search for a password that was hashed with the message digest algorithm. So the proof of concept the work is demonstrate the result for various password lengths suitable to run within reasonable amount of time, and compare performance with the sequential implementation of bruteforce attack in an FPGA

Last modified: 2021-03-30 16:03:00