Renovated 32 Bit ALU Using Hybrid Techniques

In this modern world to increasing the demand for enhancing the ability of processors, is a challenging one. The most preferred module of a CPU is ALU which executes the mathematical and digital transactions. This multi-roled ALU circuit can conditionally perform various functions depending on control inputs. In this project, by using Efficient Vedic mathematics and refurbished approximate adder to form a 32 bit Efficient ALU. The major target of this works is to get Efficient ALU by reducing the area, power, and delay. So here used unique and earliest techniques of Vedic mathematics and which is also modified and to form Efficient Vedic multiplier. This efficient Vedic multiplier eliminates the unwanted steps and remaining procedures used by CSA. It reduces the hardware complexity of speed and area, it leads to decreasing the propagation delay in the chip. Approximate carry look-head adder contributes better delay and power reduction compared to other approximate adders. Delay, power, area of this proposed method of paper calculated by using Xilinx 14.7