Design of Low Power Two Stage CMOS Operational Amplifier

The trend towards low voltage low power silicon chip systems has been growing quickly due to the increasing demand of smaller size and longer battery life for portable applications in all marketing segments. The supply voltage is being scaled down to reduce overall power consumption of the system. The objective of this project is to implement the full custom design of low voltage and low power operational amplifier. In this paper a well defined method for the design of a two-stage CMOS operational amplifier is presented. The op-amp which has been designed, exhibits a unity gain frequency of 8MHz, a gain of 70dB with 750 phase margin and power consumption is 19.5& mu; W. The simplest frequency compensation technique employs the Miller effect by connecting a compensation capacitor across the high-gain stage. Both the theoretical calculations and computer aided simulation analysis have been given in detail. Design has been carried out in Tanner tools. The simulation results in a tsmc 0.18um CMOS process from a 1.8V voltage supply demonstrate the designed has a gain 70dB.