A Novel Pass Transistor Logic Based Pulse Triggered Flip-flop with Conditional Enhancement

For the past several years, much progress has been made in Low power VLSI Design. In this paper; we propose a novel low-power pulse-triggered flip-flop (FF) design with conditional pulse enhancement scheme. Pass transistor logic based AND gate is used for pulse generation which reduces circuit complexity and enhances faster discharge. The transistor sizes of the delay inverter and pulse-generation circuit are reduced for power saving. Simulation is performed for various pulse-triggered flip-flops to demonstrate the effectiveness of our proposed design using ami.05nm technology in Mentor graphics.