Design and Analysis of Energy Efficient Semi-Serial Link for On-Chip Communication

Now a days in network-on-chip (Noc) different type of communication links are used like parallel, serial and semi-serial links. In this project low energy semi-serial on-chip communication link is designed. In this project protocol used for this proposed semi-serial link is defined. And key elements of this semi-serial link communication like serializer, deserializer, driver, receiver, and data validity decoder are designed. The energy efficiency of the proposed semi-serial link, (which consists of bit-serial links in parallel), mainly comes from the sharing of the novels serializers control circuit among the bit semi-serial links. In addition the integration of pulse signaling with wave-pipelining, the use of new low-complexity data decoding logic causes for the power reduction. The links are designed and simulated using cmos 180nm, 120 and 65 nm technologies in microwind 3.1 cadtool. When technology scale down from 180nm to 65nm, power decreased from 22.216mw to 10.464mw, delay decreased from 0.247ns to 0.115ns and power-delay product varies from 5.487pw-sec to 1.203pw-sec.