Interconnect Delay and Power Optimization Using Schmitt Trigger as Alternate Approach to Buffer Insertion

In this thesis, we address the interconnect problem in the deep sub-micron (DSM) regime. In VLSI interconnects to restore the input signal affected by the parasitic buffers are placed in between interconnects. But buffers has a certain switching time that contribute the overall signal delay and crosstalk delay. The designs of sized logic and repeater insertion for improved delay, power and placement are implemented by using both Schmitt trigger and buffer insertion. In this work replacement of sized logic with buffers with Schmitt trigger based on sizing is proposed for the signal restoration and to reduce delay. Because of adjustable threshold voltage Vth of Schmitt trigger the delay and power can be reduced in interconnects when compared to buffers. HSPICE simulations are carried out for the different PTM based on sized logic shows that Schmitt trigger with sized logic gives 12.45 % less delay when compared to buffer sized logic and also average power reduced to 5.09 % in case of Schmitt trigger when compared to sized logic of buffer.