Analysis of Low Power Test Pattern Generator by Using Low Power Linear Feedback Shift Register (LP-LFSR)

This paper proposes a low power Linear Feedback Shift Register (LP-LFSR) for Test Pattern Generation (TPG) technique with reducing power dissipation during testing of VLSI circuits through the built in self test (BIST) approach. The objective of the BIST is to reduce power dissipation without affecting the fault coverage. This proposed test pattern generator reduces the switching activity among the test patterns at the most. In this approach, the single input change patterns generated by a counter and a gray code generator are ExclusiveORed with the seed generated by the low power linear feedback shift register [LP-LFSR]. Thus the proposed method significantly reduces the power consumption during testing mode with minimum number of switching activities using LP-LFSR in place of conventional LFSR in the circuit used for test pattern generator. The simulation and synthesis results were carried out with the modelsim-altera 6.5b (Quartus-II 9.1) version and Xilinx ISE design environment 12.1 version respectively. The simulation results show the comparison of reduced number of transitions between the test patterns, which are generated by the proposed and existing systems. From the implementation results, it is verified that the proposed method gives better power reduction compared to the exiting method.