A Survey on Buffered Clock Tree Synthesis for Skew Optimization

Buffered clock tree synthesis has become increasingly critical in an attempt to generate a high performance synchronous chip design. Skew optimization includes the satisfaction of slew constraints and signal polarity. Clock tree approach features the clock tree construction stage with the obstacle aware topology generation algorithm, balanced insertion of candidate buffer positions and a fast heuristic buffer insertion algorithm. With an overall view on obstacles to explore the global optimization space, CTS approach effectively overcomes the negative influence on skew which is brought by the obstacles. A look up table was built through NGSPICE simulation to achieve accurate buffer delay and slew which guarantees overall skew optimization. The accuracy of look up table is demonstrated through huge skew reduction. Additionally, wire length of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulses at the synchronizing elements of the system.