High Speed Advanced Encryption Standard Using Pipelining

In this paper we have proposed high throughput by swapping the AES algorithm internal stages in this proposed work shift row is operated before sub bytes (substitution bytes). In this proposed operation the AES encryption operation will not effect, with this process is streamlines the processes a 4 block of data rather then 16 block. The advantage of this is we can save area. This process repeats for 10 cycles and with the help of this we can encrypt 128 bits data with higher throughput. We have evaluated this performance of higher throughput and hardware area in Xilinxs 12.2 vertex 4 XC4VFX140-11FF1517.