Implementation of High Throughput Radix-16 FFT Algorithm

The extension of radix-4 algorithm to radix-16 to achieve the high throughput of 2.59 giga-samples/s for WPANs. We are also reformulating radix-16 algorithm to achieve low-complexity and low area cost and high performance. Radix -16 FFT is obtained by cascaded the radix -4 butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to its optimized pipelined structure. The proposed radix-16 FFT algorithm is area-efficient with high data processing rate and hardware utilization efficiency. The multiplier cost of the proposed FFT algorithm is less than that of the previous FFT structures in FFT applications. Although the radix-16 FFT algorithm has less computational complexity, the control circuit of the direct radix-16 architecture for implementing radix-16 FFT is very complex. Thus, the efficient simplified radix-16 structure, with four radix 4 structures pipelined model, will be applied to radix-16 FFT algorithm, so that the extension is easily applicable