VHDL Implementation of Built in Generation of Functional Broadside Tests

Functional broadside tests are two-pattern scan-based tests that avoid over testing by ensuring that a circuit traverses only reachable states during the functional clock cycles of a test. In this paper, we test the S27 sequential circuit by using Built in Self Test. The hardware was based on the application of primary input sequences initial from a well-known reachable state. Random primary input sequences were changed to avoid repeated synchronization and thus yield varied sets of reachable states by implementing a decoder in between circuit and LFSR. This paper shows the on chip test Generation for a bench mark circuit using simple fixed hardware design with small no of parameters altered in the design for the generation of number of patterns. If the patterns of the input test vector results a fault simulation then circuit under test is going to fail.