An Efficient Design for Reduction of Power Dissipation in Johnson Counter using Clock Gating

In this paper, a new method for minimizing power dissipation in 4-bit Johnson up-down counter is proposed. In this design, we have used a dual dynamic pulsed flip-flop (DDFF) [1], which supports embedding a logic module (DDFF-ELM) and a power saving technique, namely, clock gating [2] is used. We have used DDFF because it is power efficient compared to other flip-flops in the literature. We have used digital schematic editor (DSCH) for designing, simulation and layout generation is done using Microwind. From the simulation results, it is observed that power dissipation is reduced by 33.9 %.