Implementation of Enhanced Cache Controller with Multi-Sized Outputs

The major role of cache controller is reduction in the data transfer access time between the CPU and cache. The controller which is capable of handling a system with many cores is designed. It is also capable of giving multi-sized output like 1, 2, 4, 8 and 16 bytes. The operation of this controller is defined by 6 different states like Fetch Data, Read Cache, Write Cache, Read Memory, Write Memory and Give Data. The controller can be used for different ways of caches. The design is developed using Verilog HDL. A test bench is also developed to test the functionality of the design.