An Efficient Design of Advanced Encryption Algorithm with FPGA

A FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is performed using a reconfigurable 32-bit MicroBlaze processor embedded in the FPGA chip using RS232 to interface with PC to obtain a prototyped data encryption/decryption system. The iterative looping approach with block and key size of 128 bits, lookup table implementation of S-box will performed. Simulation results, data summary results are carried out with previous reported designs.