Carry Select Adder Implementation using Asynchronous Fine Grain Power Gated Logic

This paper presents a low power logic family, called asynchronous fine-grain power-gated logic (AFPL). Each pipeline stage is comprised of the logic function called efficient charge recovery logic (ECRL) gatesand a handshake controller. ECRL gates have negligible leakage power dissipation. By incorporatingpartial charge reuse (PCR) mechanism the energy dissipation required to complete the evaluation of an ECRL gate can be reduced. Moreover, AFPL-PCR adopts a C*-element, in its handshake controllers. To mitigate the hardware overhead of the AFPL circuit, circuit simplificationtechniques have been developed.