Design and Implementation of Power Efficient 8:1 Multiplexer Based on Adiabatic Logic

The increasing speed and complexity of todays designs implies a significant increase in the power consumption of the very- large scale integration (VLSI) of chips. To meet this challenge, researchers have developed many different design techniques to reduce the power. Adiabatic switching principle is one of the important circuit design technique, which reduces the power consumption compared to conventional CMOS. This paper presents a 81 multiplexer based on adiabatic switching principle that uses a pair of complementary split-level sinusoidal power supply clocks for digital low power applications. Some standard adiabatic logic styles like PFAL, ECRL, 2n2n2p are investigated, but the proposed logic is better. The simulation is carried out in TSPICE software at 0.5 m CMOS technology for frequency range 200MHz 800MHz