Prototype Design of DSP Processor using Multiplier Oriented Reconfiguration

Most embedded systems developments in recent years have been primarily based on hardware level reconfiguration. Reconfigurable architecture requires many processing elements and configuration switches and it increases complexity of the design, but at the same time improves flexibility. Reconfiguration in ALU design can significantly increase speed of operations. In order to achieve high through put rate in ALU, an efficient switching between elements and also a significant reduction in clock cycle is required. In this work a prototype design of a DSP processor with some improvements done on the multiplier based reconfiguration module architecture to increase the throughput rate. For data sensitive computations in digital signal processing the proposed reconfigurable ALU could be used. The task for the DSP operations will be shared into the proposed cores as per time and size demand.