FPGA Implementation of Pipelined Architecture of Floating Point Arithmetic Core and Analysis of Area and Timing Performances

The aim of this paper is FPGA implementation of architecture of floating point arithmetic core and analysis of area and timing performances of that arithmetic core. The basic concept behind designing such a core is to optimally utilize the algorithms of floating point arithmetic operations, i.e., addition, subtraction, multiplication and division and to enhance the operational speed of these calculations in order to determine the better code amongst them in order to use it in future to increase the processor efficiency. The simulation has been carried out on Modelsim (Student edition) EDA tool 10.0c and synthesis has been carried out on ISE Design Suit EDA tool 14.4.