Developing Throughput in Associative Memory Using Phase Overlapped Processing Scheme

A Content Addressable Memory (CAM) is a special sort of search memory utilized in high speed seeking appliance. This paper establishes a Phase overlapped processing scheme to increase the throughput and low energy content addressable memories. Traditionally, the power consumption in CAMs due to high switching activity is considered as the main limiting factor in CAM. In order to diminish the switching activity of the Memory Cell in Binary Content Addressable Memory (BCAM), 10T SRAM is implemented and also introduces a power consumption minimization technique for Ternary Content Addressable Memories (TCAMs) which are used mainly for high-speed packet transmission and classification over routers and switches in network. The self-timed word circuit is independently manipulated by a locally generated control signal, it reducing the power dissipation of global clocking. This tolerates the circuits to be in the necessary phase for their individual local operation contains evaluate or precharge, which enormously diminish the cycle time. As, a design example, CAM is implemented and evaluated by Tanner simulation under a 130 nm CMOS technology.