Design of Shift Register using Pulsed Latches to Reduce Area and Power Dissipation

This paper proposes the method to design shift register using TSPC pulsed latches and clock generator circuit with GDI AND gate and one delay cell.The proposed method reduces area and power dissipation by using 130nm Mentor Graphics tool. Here, the proposed method is compared with the two conventional methods of shift registers.In one of the conventional methods, shift register is designed by using PPCFF (Power-PC style flip-flop).The flip-flop based shift register requires one clock signal for each flip-flop for its operation. In the second method, the shift register is designed by using SSASPL (Static Differential Sense Amplifier pulsed latch) and clock generator circuit with simple AND gate and some delay cells. For the operation of pulsed latch, a pulsed clock signal (a part of clock signal) is sufficient.