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Implementation of Logic Gates using the Dual Mode Logic and their Applications

Journal: International Journal of Scientific Engineering and Research (IJSER) (Vol.5, No. 7)

Publication Date:

Authors : ; ;

Page : 374-379

Keywords : Basic gates; D- Flip flop; TSPC-D Flip flop; Johnson counter.;

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In this paper, a Johnson up-counter was designed by using the different types of flip flops. Here the D-flip flop was designed using the DML type_A NAND gate, and TSPC flip flop using the DML( Dual Mode logic) logic inorder to reduce the power dissipation. The TSPC_DML flip flop has less power compared to the D-flip flop. The Dual Mode Logic (DML) family provides a novel approach to providing this capability by introducing two configurable operating modes, static and dynamic. The dual mode logic gates has very low-power dissipation with moderate performance in the static mode of operation.The proposed TSPC D-flip-flop in which the number of transistors are reduced from 11 transistors to 5 transistors. As number of transistors are reduced in occupies less area and also the power will be reduced compared to the conventional TSPC (True single phase clock) D-flip-flop.

Last modified: 2021-07-08 16:10:09