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Review for Design Considerations of SAR ADC in CMOS 32 NM Technology

Journal: International Journal of Science and Research (IJSR) (Vol.11, No. 4)

Publication Date:

Authors : ; ; ;

Page : 516-519

Keywords : ADC; SAR; CMOS 32nm Technology; Low power; comparator; sample-and-hold;

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Analog-to-Digital Converters (ADCs) are key components for the design of power limited systems, in order to keep the power consumption as low as possible. Among all ADCs, Successive Approximation Register (SAR) ADCs are mostly used due to their simpler structure, fewer analog blocks, smaller area, and lower power consumption. This review paper is focuses on a study to summarize developments in SAR based ADC. It also focuses on the new CMOS 32nm technology and on some major designing components, parameters like area, power, current and techniques analysis like parametric, delays, speed critical paths and cross talks while designing a SAR ADC.

Last modified: 2022-05-14 21:04:25