Power and Area Efficient Systematic Logic Cell Design for Processing Applications

In this paper, a Systematic Cell Design Methodology(SCDM) based on transmission gate in the category of hybrid-CMOS Logic style is proposed . (SCDM), which is an extension of Cell Design methodology(CDM), plays the essential role in designing efficient circuits. In this methodology, designer utilize various basic cells, including three independent inputs and two complementary outputs. XOR/XNOR circuits are proposed with high driving capability, full-balanced full-swing outputs and low number transistors of basic structure, high performance, operating at low voltages and excellent signal integrity. As an especial feature, the critical path of the presented designs consists of only two transistors, which causes low propagation delay. All simulations have been performed with TSMC 0.125-μm technology, in optimum state of the circuits from viewpoint to achieve the minimum power-delay product (PDP) and of transistor sizing. They also outperform their counterparts exhibiting 17%–53% reduction in average energy delay product .The simulation results demonstrate the delay, power consumption and power-delay product (PDP) at different supply voltages ranging from 0.8V to 1.6V.