SYNTHESIS OF MULTIPLE-OUTPUT TRANSISTOR-LEVEL USING CAD TOOL

The important goal of very large scale integration design synthesis tool is to minimize the number of transistors required to implement circuits with minimal transistors count. The proposed approach allows extensive bridging, setting aside the traditional series-parallel design style. The proposed theory modifies expressions into sum of products (sop) form for individual output even considering don't care terms. This produces a transistor network with minimum number of transistors implementing a user specified bond on number of transistors in series while not considering long charge paths to jointly represent output.