COMPARATIVE ANALYSIS OF VEDIC & ARRAY MULTIPLIER

Most of the today's real time signal processing algorithm includes multiplication as its processing heart. It is most important arithmetic unit in Microprocessor & DSPs. The speed & power consumption & packaging of the processor is mainly determined by its multiplier. Two important parameters associated with multiplication performed in Processors applications are latency and throughput. Latency is the “real delay of computing a function”. Throughput is a measure of “how many computations can be performed in a given period of time”. The execution time of most processor is dependent on its multipliers, and hence need for high speed multiplier arises. The objective of this manuscript is to simulate both Vedic & Array multiplier for different bit lengths i.e. two, four , eight & sixteen bit on Model Sim-Altera 6.6d (Quartus II 11.0sp1) Starter Edition using VHDL language and then implementation them on Xilinx 14.4 with family Spartan6, device as XC6SLX45, package CSG324 with speed grade of -3 for comparative analysis.