Level Converting Retention Flip-Flop for Low Standby Power Using LSSR Technique

In VLSI we have an exponential increase of leakage power due to scaling of threshold voltage. We have both active power and standby power dissipation. It is important to reduce standby leakage in case of small battery operated devices. A flip-flop will hold the logic only in the active mode of operation. But a retention flip-flop will hold the data even in the standby mode of operation, with continuously given supply exclusively for the retention latch. A level converting retention flip-flop is used to turn off the voltage regulator in the standby mode of operation, to reduce standby power dissipation. The proposed retention flip-flop will reduce the standby power dissipation, in which the retention latch was designed using LSSR (LECTOR (Leakage Control transistor) Stacked State Retention) technique. The slave latch of the proposed retention flipflop constructed by using thick oxide transistors, i.e. the length of the transistor has taken as 350nm. The architecture of retention flip-flop depends on VDD,IO scheme, in which VDD,core and VDD,IO are two different voltages. VDD,IO is higher than the VDD,core. The level up conversion from VDD,core to VDD,IO is achieved by NMOS pass transistor level conversion scheme, which is based on an always low signal transmission technique. The proposed retention flip-flop reduces the standby leakage compared to LECTOR based retention flip-flop, with small increase in area. The proposed retention flip-flop was designed in 130nm technology with 1.2V and 2.0V for core latch and retention latch respectively. The operating frequency is 20MHz, and the standby power is 255.8619pW