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HIGH DATA-RATE SDR FOR V2V COMMUNICATION USING XILINX SYSTEM GENERATOR

Journal: International Journal of Mechanical Engineering and Technology(IJMET) (Vol.9, No. 4)

Publication Date:

Authors : ; ;

Page : 686-694

Keywords : SDR; MATLAB/Simulink; XILINX-ISE; DDS (Direct Digital Synthesis); system generator; QPSK modulation-demodulation.;

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Abstract

Vehicle to vehicle (V2V) communication systems need RF networks in which vehicles and roadside units act as communicating nodes, providing each other with information, such as safety warnings and traffic information. They can be effective in avoiding accidents and traffic congestion. Both types of nodes are dedicated shortrange communication (DSRC) devices. DSRC works in 5.9 GHz band with a bandwidth of 75 MHz and approximate range of 300 m using SDR. SDR (Software Defined Radio) generally refers to the transceiver systems in which the entire physical layer is implemented in software using various DSP algorithms. They have the ability to tune over the frequency ranging from 25MHz to 1.75GHz which makes them more versatile. SDRs are used in wireless and Satellite Communication (SATCOM) [1] domains. They are many enhanced systems compared to the traditional hardware based systems in terms of cross-functionality, cost and flexibility. They are suitable for today's requirement of smaller and constantly changing bandwidths. In this paper, we have used QPSK modulation technique to transmit and receive digital data. The modulator and the demodulator are simulated in a MATLAB / Simulink environment using a Xilinx system generator. An SDR consists of various modules which include channel sources of SDR, transmitter block, receiver block, and the most important the channelizers in the receiver. The channelizers are used to select a range of required frequencies from a particular RF band. Later these frequencies are used for modulation and demodulation purpose. The objective of this project is to assemble an SDR block and simulate it in MATLAB/Simulink and to perform the design implementation in ZED board using Xilinx ISE Design Suite/VIVADO.

Last modified: 2018-12-13 18:49:22