Power Efficient Viterbi Decoder Using Trace Back Architecture

Error correction is an integral part of any communication system and for this purpose, the convolution codes are widely used as forward error correction codes and for their decoding at the receiver end viterbi decoders are employed. Viterbi Decoders are employed in digital wireless communication systems to decode the convolution codes which are the forward correction codes. The decoders are quite complex and dissipate large amount of power. The high speed and small area are two important design parameters i high speed viterbi decoder has been designed using track back architecture. The proposed viterbi decoder has been designed with Matlab, simulated with Xilinx Xilinx DSP Tool, synthesized with Xilinx Synthesis results show that the proposed design can operate by consuming considerably less resources on target device