Verilog Implementation, Synthesis & Physical Design of MOD 16 Counter

In this paper, MOD 16 up counter has been implemented using Cadence front end tools. Verilog RTL has been used for writing the code of counter. The functionality of counter has been tested by writing the testbench of counter and observing its output waveform. Synthesized circuit and gate level netlist is generated by the synthesis tool. It also gives area, power and timing report which is satisfactory for the current design. Finally, physical design of counter is done which includes stages like floorplanning, power planning, placement, clock tree synthesis and routing. Setup time and hold time violations have been checked after routing stage. Total negative slack and worst negative slack have been found to be zero. Total power dissipation is 11767.597 nW and total area occupied by 13 cells of synthesized circuit is 88.200 units.