A Memory Implicit Self-Reconditioning Based On Configuarable Substitutes

We present an MISR generator which automatically generates register transfer level MISR circuits for SoC designers. There is growing need for ingrained memory implicit self reconditioning system (MISR) due to the introduction of more and more system-on-chip (SoC) and other highly integrated products, for memories, and repairing embedded memories by Conventional off-chip schemes is expensive .The MISR circuit has a scalable architecture, and it implements an enhanced version of our EP algorithm for efficient 2-D repair .A typical BISR draft requires circuit modules that perform built-in self-test (BIST), implicit redundancy analysis (IRA), real-time address remapping, and so on. The faulty cells can be repaired immediately after manufacturing but still unused substitutes can serve for replacement during lifetime of systems on chip making them more fault-tolerant.the repair process based testing outcomes and on the repair analysis is done by external devices or by internal blocks integrated directly on chips. The proposed MISR circuit is small, and it supports at-speed test without timing-penalty during normal operation. With its low overhead a