Performance Analysis of Voltage Scaled Low Power Clock Distribution Network with Different Frequencies

Clock distribution networks forms an inherent part of any digital circuit. It use a large part of the total circuit power, which is not worthy. Different techniques are employed up till now to reduce the clock power. In this paper we have to demonstrate how clock power can be reduced significantly by distributing it at reduced supply voltage and analyse the power consumption of clock distribution network with different frequencies like 100 MHz, 200 MHz, 250 MHz, 400 MHz, and 1 GHz etc. The clock distribution network is designed and simulated in 180 nm technology. Achieving power reduction of about 52 %, 48 %, 44 %, 38 %, 27 %and26 %respectively