IMPLEMENTATION OF AES ENCRYPTION IP

Security plays a vital role in Digital Circuits and Applications. The Integration of Crypto processors with the hardware is inevitable and must. Crypto processors are used in military application, ATM, smart cards, SIM cards, automobiles and so on. In this project We Implemented AES ENCRYPTOR IP, Intellectual property (IP) is a reusable logic unit or layout design that is normally developed with the idea of licensing to multiple vendors for using as building blocks in different chip designs. The IP developed in the project performs 128-bit AES encryption and the technology involved is Synopsys's SAED 32nm static CMOS technology operating at nominal voltage of .95 V, temperature of-40° C and process of .99 which is a global slow corner and the design is finely tuned on Power, Performance, AREA (PPA) parameter. The target frequency for this AES Encryption IP is 0.714 GHz. Since the project deals with the nano transistors, the CAD tools are used for In-House deigning, Synopsys VCS and Icarus Verilog is used to simulate SOFT IP, Synopsys DC compiler is used to synthesis the FIRM IP and to Implement the final HARD IP Synopsys ICC compiler is used. Verilog Hardware descriptive language (HDL) is used to code the SOFT IP.