Implementation of Restartable BIST Controller for Fault Detection in CLB of FPGA

Today Field Programmable Gate Arrays (FPGAs) are widely used in many applications. Complicated integrated circuit chips like FPGAs are prone to different types of Faults due to environmental conditions or aging of the device. The rate of occurrence of permanent faults increases with emerging technologies because of increased density and reduced feature size, and hence there is a need for periodic testing of such FPGAs. Efficient testing schemes that guarantee very high fault coverage while minimizing test costs and chip area overhead have become essential [1, 11]. The Configurable Logic Blocks (CLBs) are the main logic resources for implementing sequential as well as combinatorial circuits in FPGA [8]. Built-In Self-Test (BIST) is a design technique that allows a circuit to test itself [2]. Here, We are implementing a restart able logic BIST controller for the configurable logic blocks by using the resources of FPGA itself [7, 10]. The design exploits the reprogramability of an FPGA to create the BIST logic by configuring it only during off-line testing. The technique achieves the testability without any extra burden as the BIST logic disappears when the circuit is reconfigured for its normal operation. The proposed technique implemented through VHDL, after verifying the simulation results the code will be synthesized on Xilinx FPGA. Modelsim Xilinx Edition (MXE) and Xilinx ISE will be used for simulation and synthesis respectively. Xilinx FPGA board will be used for testing and demonstration of the implemented system. The Xilinx Chipscope tool will be used to test the FPGA inside results while the logic running on FPGA [3, 4]. As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test costs and chip area overhead have become essential. As the complexity of circuits continues to increase, high fault coverage of several types of fault models becomes more difficult to achieve with traditional testing paradigms [9]. Integrated circuits are presently tested using a number of structured designs for testability (DFT) techniques. These techniques rest on the general concept of making all or some state variables directly controllable and observable.