Display Area and Character Organization and Control for BZK.SAU.FPGA Micro Computer Architecture

In order to obtain images in the display area, the color and synchronizing signals control signals of the VGA display hardware display hardware should be managed. Desired image is obtained with controlling these signals for lightening or deflating of pixels the display hardware. In this study, display controller that allows the formation of the image on the screen by controlling these signals was designed at logic gate level. BZK.SAU.FPGA mikro computer architecture was used and an VGA display with 640×480 pixel resolution was preferred for this purpose.