Low Power Full Adder Implementation Based on Pass Transistor Technology

Addition is a fundamental for all the arithmetic operation, it is mainly used in digital signal processing architecture and microprocessor. The sum module is the core of arithmetic operation, like addition, subtraction, multiplication, division. The aim of the project is design of full adder having low power consumption and low power delay. In this project, a new hybrid 1-bit full adder is designed using both CMOS and pass transistor logic, for the purpose of reducing the no of transistors. It consists of three modules such as two XOR module and one MUX module. It is used to improving power delay product (PDP). This can be implemented by using the software Tanner EDA.